In recent years, a semiconductor integrated circuit, among others, complementary metal oxide semiconductors (CMOS), charge coupled devices (CCD), CMOS image sensors (CIS) are manufactured using techniques of preventing, at impurity doping into a microscopic region by ion doping, impurities from being doped into locations deeper than expected, due to ion channeling.
Channeling phenomenon (Hereinafter, referred to as “channeling.”) is a phenomenon in which when ions are doped substantially in parallel with the crystallographic axis or crystal planes of a crystalline material, due to the geometric arrangement of atoms forming the crystal lattice, doped ions pass through lattice spacing without colliding with the atoms composing the crystal. For convenience, the channeling can be categorized into axis-channeling along with a low order crystallographic axis such as <100> direction, and plane-channeling along with low order crystal planes such as (100) plane and (111) plane. When ion doping which causes the channeling is performed, variation in depth to which doped ions extend is great as compared to when ions are doped nonparallel with the crystallographic axis or the crystal planes.
Known technique for preventing the channeling is, typically, setting an ion beam angle, which is called Tilt angle, relative to the normal (the vertical direction) of the front surface of a wafer (semiconductor substrate) to about 3 to about 10 degrees, generally, 7 degrees to prevent the channeling.
On the other hand, when Tilt angle is not zero degree, while the channeling can be prevented, phenomenon known as shadowing occurs in an ion doping step which is performed after structures of resist and gate electrodes are formed. The shadowing is a phenomenon in which ions are not doped into a portion of the wafer that is shaded by such structures.
Non Patent Literature (NPL) 1 discloses that a portion of a wafer is shaded by a gate electrode due to errors in Tilt angle and Twist angle in a large current ion implantation apparatus, and thus ions at extension doping and source-drain doping are not performed symmetric to the wafer, ending up increasing drain current asymmetry. NPL 1 also discloses that 4-step doping is effective as a measure to this. For example, when the resist thickness is 600 nm, a portion of the wafer 73.6 nm (600 nm×tan 7 degrees) extending from the resist is shaded by the resist, and ions are not doped into the portion. To prevent this, the ion doping is performed on the structures in four directions, thereby mitigating the asymmetry of the ion doping.
On the other hand, in recent semiconductor devices, some transistors have channels not only in parallel with and perpendicular to but also 45 degrees tilted relative to a notch direction. In that case, the ion doping needs to be performed in eight directions. In other words, it is essential to develop an ion doping technology which can minimize the shadowing due to the structures such as resist and gates, and inhibiting the channeling in the ion doping.
Various problems occur in a conventional method, with use of an ion beam having Tilt angle set to 7 degrees, which performs the ion doping in four steps or eight steps, rotating a wafer so that the ion beam is not shaded by the structures such as resist and gates. As mentioned earlier with respect to the asymmetry of the ion doping due to the shadowing of structures, even if the ion doping is performed in multiple steps, for example, four steps, at least one ion doping is not performed on a portion that is shaded by the structures, as compared to that ion doping is performed four times on a portion that is not shaded by the structures. After all, ions are doped, undesirably, three times on the portion shaded by the structures while ions are doped four times on the portion that is not shaded by the structures. In other words, the asymmetry of ion doping is reduced but not entirely eliminated.
Moreover, in the ion doping in multiple steps, Twist angle of the wafer needs to be changed at every doping (the wafer is rotated by 90 degrees for four steps, and rotated by 45 degrees for eight steps). Because the doping step is divided into sub-steps in addition to these operations, the beam current is reduced to provide uniformity, ending up significantly decreasing productivity. Because of this, a method is proposed which does not perform the ion doping step in multiple steps, and provides, to inhibit the channeling, the front surface of a silicon substrate with a desired Off angle (wafer cutting angle from silicon ingot) for use in manufacturing the semiconductor device (see Patent Literature (PTL) 1 and NPL 1, for example).
PTL 1 discloses that the channeling can be inhibited by using a silicon substrate which has a silicon front surface having Off angle of 3.5 to 10 degrees from (100) plane toward a plane perpendicular to (100) plane, and performing the ion doping perpendicular to the silicon front surface. NPL 1 assumes that the control precision of Tilt angle in wafer-plane by the ion implantation apparatus has an error of ±1.6 degrees, and further assumes that angle error due to the setting of the wafer to the ion implantation apparatus is ±1 degree. Moreover, NPL 1 assumes that an error in controllability of Off angle of the wafer is ±0.5 degree.
The assumption requires Off angle to be 4 degrees or greater, and additionally, considers the ion beam divergence in the wafer-plane, in addition to the angle error of the ion implantation apparatus which is 1.6±1 degrees. Thus, Off angle relative to the plane ends up being relatively large ranging from 4 degrees to 10 degrees.
NPL 1 considers not only the channeling due to Tilt angle but also the plane-channeling, and determines the direction of Off angle, based on at least two directions that are perpendicular to (100) plane. The ion doping is performed perpendicular to the front surface even if Off angle is largely tilted. Thus, it seems that no portion of the wafer is shaded by the structures such as resist and gate electrodes. However, NPL 1 discloses that an error in the beam angle in the wafer-plane in the ion implantation apparatus is ±1.6 degrees, and the angle error due to the setting of the wafer is ±1 degree. Thus, the technique disclosed in NPL 1 may require multi-step ion doping to eliminate the asymmetry caused by the angle error in the ion implantation apparatus.